1. Field of the Invention
The invention relates to a Dynamic Random Access Memory (DRAM) controller and DRAM control method, and more particularly to a DRAM controller and DRAM control method capable of compensating for performance degradation due to a Read-Modify-Write (RWM) operation in response to a partial write request.
2. Description of the Related Art
Currently, Dynamic Random Access Memory (DRAM) is widely used for data storage. Generally, read/write operations are controlled by a DRAM controller. FIG. 1 is a block diagram showing a conventional DRAM controller. As shown in FIG. 1, the DRAM controller 100 includes a control unit 101 and a merge unit 102, coupled to the DRAM 200 through a command bus 105 and a data bus 106, respectively. In response to a read/write request from a central processing unit (CPU) (not shown in FIG. 1), the DRAM controller 100 accordingly controls the read/write operation of the DRAM 200; thereby controlling data, requested by the CPU, to be read out from or written into the DRAM 200.
For DRAMs (such as the DRAM 200 shown in FIG. 1) supporting Error Correction Code (ECC), when receiving a partial write request, the DRAM controller 100 has to perform a Read-Modify-Write (RMW) operation on the DRAM 200 so as to correctly calculate an ECC for the data to be written into the DRAM 200. To be more specific, as known by the person with ordinary skilled in the art, the minimum data unit for the CPU to write data into the DRAM is 1 byte. However, the bandwidth of the bus disposed between the CPU and the DRAM is usually larger than 1 byte. As an example, the bus bandwidth may be 8 bytes. The request issued by the CPU to write data with a data size less than the bus bandwidth is called a partial write request. Meanwhile, the request to write data with a data size equal to the bus bandwidth is called a normal write request or simply called a write request. Because the ECC error correction is performed based on 8 bytes as a minimum data unit, for data to be written, which is requested via a partial write request (for example, the partial write data is the data with 1 byte data size), calculation of the ECC is incorrect. To solve this problem, when receiving a partial write request, the control unit 101 sends out a read command via the command bus to the DRAM 200 so as to read out data with a burst length, including the data on the partial write address of the partial write request, to the merge unit 102 (read operation). Next, the merge unit 102 merges the read data with the partial write data corresponding to the partial write request. That is, the merge unit 102 replaces the data, on the partial write address of the partial write request, read out from DRAM by the partial write data (modify operation). Finally, the control unit 101 writes the merged data to the DRAM 200 (write operation) so as to complete the partial write request.
As previously described, for a partial write request, three operations have to be successively performed. Therefore, the time required for a partial write request is long. When the DRAM controller receives multiple partial write requests within a short period of time, DRAM performance is seriously degraded.
Therefore, a novel DRAM controller and DRAM control method is highly required to compensate for performance degradation due to the RWM operation in response to a partial write request.